ELEC 101
Prof. Rich Kozick
February 26, 1998

Laboratory 5
Thevenin Equivalent Circuit Models

In this lab, we will develop Thevenin equivalent circuit models for a digital logic gate. We will begin by learning how to read the data sheet for the digital logic gate.

You may find it useful to review the electronic lesson on Thevenin equivalent circuit models in the Exploring Engineering program.


1. NAND Logic Gate

The digital logic operation that we will consider is NAND, which is short for "NOT - AND". The truth table for NAND is as follows. The two states in digital logic are referred to in several ways, including "1" and "0", "high" and "low", or "H" and "L". 
  INPUTS  OUTPUT
   A  B     Y

   0  0     1
   0  1     1
   1  0     1
   1  1     0
Your lab kit includes a chip labeled 7400 that contains four NAND gates. (The actual label on the chip may be 74LS00 or 74ALS00.) The data sheet that describes the 7400 chip is attached. (You can view data sheets for a variety of NAND gate circuits at
http://www.fairchildsemi.com/catalog/Digital_Gates_NAND.html

Before lab, please read the attached data sheet for the 7400 chip and try to answer the following questions.

  1. What is the allowed range of input voltage levels to represent a 0 or logical low?
  2. What is the allowed range of input voltage levels to represent a 1 or logical high?
  3. At the output of the logic circuit, what range of voltage levels are produced to represent a 0 (low) and a 1 (high), respectively?
  4. Suppose that the output of a NAND gate is connected to the input of another NAND gate. When the first NAND gate output is a 1, how much current flows between the gates? In which direction does the current flow? (The convention for the sign of the current in the data sheet is that positive current flows into the device.)
  5. Repeat the previous question when the first NAND gate output is a 0.
  6. Is there any limit on how many gates a given output can be "fanned-out" to? Is the limit more restrictive in the case of a 0 output or a 1 output? Please explain.


2. Thevenin Models for the 7400 NAND Gate

Since the 7400 NAND gate circuit produces a voltage at its output to represent logical 0 and 1, we might expect that a Thevenin circuit model can be constructed that describes how the output voltage changes when various load currents are drawn. Consider first the case when the NAND gate output is a 1. Perform measurements to determine the Thevenin model for the NAND gate in this state. You should obtain about 10 points on the load voltage-load current graph. Be sure to take data along the entire range of the plot, from open circuit to near short circuit.

I have prepared a MATLAB program dplot.m to help you plot your data and obtain the Thevenin model parameters by fitting a straight line to your data. Save the program dplot.m on the PC, start MATLAB on the PC, and open the file dplot.m in the editor. Enter your data, and follow the instructions in the program.

Can your data be well-approximated by a straight line? (You may want to use only a subset of your data to obtain the Thevenin model.) What is a reasonable Thevenin model for the NAND gate producing a 1 at its output?

Discuss your results with the instructor, and then perform the following.

  1. According to the data and Thevenin model that you constructed above, how much current must be drawn from the NAND gate output so that the output voltage is no longer within the limits of a logical 1?
  2. Develop a Thevenin model for the NAND gate output for the case when the NAND output is a logical 0. Is the model different from the case when the NAND output is a 1?
  3. Is it possible to obtain a Thevenin model for the input to the NAND gate? You might begin to answer this question by measuring the open-circuit voltage at an input to a NAND gate on the 7400 chip. What is the Thevenin model for this case?
  4. Can you apply your Thevenin models to explain the "fan-out" limit discussed in Section 1 of this lab?